The present invention relates to emulation of logic and memory circuits; in particular, the present invention relates to emulation of logic and memory circuits having timing signals of multiple asynchronous domains.
In logic circuit design, a logic emulation system is often used to verify the correct functional operation of a user design. One example of a logic emulation system is the field programmable gate array (FPGAs) based emulation system described in U.S. Pat. No. 5,596,742, entitled xe2x80x9cVirtual Interconnections for Reconfigurable Systems,xe2x80x9d issued on Jan. 21, 1997 (xe2x80x9cVirtual Interconnection Patentxe2x80x9d). The Virtual Interconnection Patent is hereby incorporated by reference in its entirety to provide background of the art.
FIG. 1 illustrates exemplary emulation system 100 for logic verification in an in-circuit emulation configuration. As shown in FIG. 1, emulation system 100 includes emulation hardware 5, which consists of FPGAs 12 connected (as indicated by element 14) in a predetermined topology (e.g., 2-dimensional mesh) and memory system 6, host computer 2 and target system 4. Software in host computer 2 partitions a user circuit into individual partitions, each partition to be configured into an FPGA for emulation. Typically, during emulation, a control program running in host computer 2 controls the emulation of the user circuit in emulation hardware 5. In one form of emulation, known as xe2x80x9cin-circuit emulation,xe2x80x9d target system 4 provides input stimuli to, and receives output signals from emulation hardware 5. Often, target system 4 provides one or more clock signals (xe2x80x9cuser clock signalsxe2x80x9d) to operate the user circuit implemented in emulation hardware 5. In the system described in the Virtual Interconnection Patent, logic is evaluated and the results are communicated in emulation hardware 5 using a high-speed system clock signal (xe2x80x9cvirtual clockxe2x80x9d). In that system, multiple signals are pin-multiplexed and pipelined between FPGAs.
In one emulation system, to ensure causality in the user circuit is reflected in the circuit configured into emulation hardware 5, and to avoid timing problems (e.g., violation of a xe2x80x9chold timexe2x80x9d requirement), signal transmission among FPGAs are scheduled in space and time. Such a scheduling scheme is described, for example, in the paper xe2x80x9cTIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire(trademark) Compilation,xe2x80x9d by Charles Selvidge et al., published in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 25-31, 1995. A system implementing the TIERS scheduling scheme is disclosed in U.S. Pat. No. 5,659,716, entitled xe2x80x9cPipe-lined Static Router and Scheduler for Configurable Logic System Performing Simultaneous Communications and Computation,xe2x80x9d issued on Aug. 19, 1997 (xe2x80x9cTIERS Scheduling Patentxe2x80x9d). The TIERS Scheduling Patent is hereby incorporated by reference in its entirety to provide background of the art.
In the prior art, to schedule logic evaluation and the result communication among FPGAs, user clock signals are provided fixed timing relationships relative to the system clock signal, so that the user design is effectively mapped into a synchronous single clock domain. However, in modern integrated circuits, a data signal often transitions and is sampled at clock edges of multiple asynchronous clock domains. In the past, such a data signal (known as a xe2x80x9cmultiple transition and sample domainxe2x80x9d or xe2x80x9cMTSDxe2x80x9d signal) could be modeled accurately with respect to only one of those constituent domains. Further, to properly operate the emulation hardware, manual and special compilation steps that isolate individual asynchronous domains in the user design are required. However, this approach is not only difficult and time-consuming, the results are often unpredictable and error-prone.
The present invention provides methods in an emulation system to correctly model and verify user circuits having logic signals (xe2x80x9cMTSD signalsxe2x80x9d) that can transition or that are sampled in response to timing signals in more than one clock domain. The present invention can be applied to in-circuit emulation, targetless emulation, static target emulation (where the emulation provides one or more clock to the target system), co-modeling (where the model running in an emulator hardware interacts with software in the host processor), or a combination of some of the above techniques.
According to one aspect of the present invention, a method correctly transports values of an MTSD signal between a source logic module and a destination logic module by: (1) dividing the MTSD signal into related single domain signals; (2) assigning the related single domain signals to be routed through separate paths between the source and destination logic modules; and (3) causally merging the related single domain signals at the destination logic module. These logic modules can be, for example, field programmable logic arrays (FPGAs) or other programmable logic devices typically used in an emulation system. In one embodiment, the method inserts delay elements in selected paths, so that transit times in the single paths are substantially equal. In one implementation, at the destination logic module, the causal merging procedure selects as the MTSD signal value tile most recently arrived value among the values on the paths. Using these techniques, correct logic operation is ensured regardless of path delays between logic modules.
In one embodiment of the present invention, a target distance is computed. That target distance has at least the length of the longest one of separate paths. For a single domain signal between an output terminal of a source logic module and an input terminal of a destination logic module, the method ensures satisfaction of a required arrival time requirement of the single domain signal at the input terminal. The method then attempts to schedule paths of lengths less than or equal to the target distance. To facilitate scheduling of the paths, the dependency of signals between an output terminal and the input terminals that feed signal to the output terminal is traced through logic circuits within the logic module. (This method exemplifies a backward scheduling implementation; the present invention can be implemented using forward scheduling upon consideration of the principles of the present invention explained in the detail description.) The dependency relationship can be represented by a same domain depth and a multi-domain depth. To ensure proper scheduling of signals, delay elements can be inserted in the source logic module, the destination logic module, or both. The related single domain signals are dependently scheduled (e.g., scheduled together or simultaneously).
In accordance with another aspect of the present invention, a method is provided to schedule MTSD data and control signals to ensure same-domain and cross-domain timing constraints (e.g., setup and hold times) are satisfied. The problem solved involves scheduling signal arrival at a first set of input terminals of a logic module, which combinationally reach one or more data terminals of a state element, relative to a second set of input terminals of that logic module which combinationally reach one or more timing input terminals of the state element. Further, the method provides for the timing of output terminals of the logic module combinationally reached from an output terminal of the state element.
In one embodiment, a method according to the present invention includes (1) computing a minimum delay value between each of the first set of input terminals and a state element; (2) computing a maximum delay value between the second set of input terminals and the state element; (3) assigning an evaluation time for the state element; (4) assigning a required ready time at each terminal of the first set of input terminals based on the evaluation time and the minimum delay value of the terminal; and (5) assigning a ready time at each terminal of the second set of input terminals based on the evaluation time and the maximum delay value of the terminal. That method can further include (1) calculating, for each terminal in the first set of input terminals, a second maximum delay representing a delay between the terminal and each related terminal in the set of output terminals; and (2) assigning an initial ready time to each terminal based on the departure times of the terminal and the related terminal and the maximum delay value. In such a method, the ready time for each terminal of the first set of input terminals can be the greater of the required ready time of the terminal and the initial ready time of the terminal. The method can also insert delay elements between the terminal and the data terminal based on the required ready time of the terminal and the initial ready time of the terminal. To obtain a candidate evaluation time for the state element, the method can add to each terminal the minimum delay value, and then select the maximum value from these results to be the evaluation time.
When an output value of a state element feeds into the timing of another state element, such a relationship requires that the first state element is evaluated after the second state element is evaluated. The method of the present invention can be made to enforce this relationship.
In addition to latches in an emulation model, the present invention is also applicable to flip-flops in an emulation model. In one embodiment, a flip-flop can be converted to a master slave connected latch pair before applying a method of the present invention.
According to another aspect of the present invention, the present invention provides a method for scheduling signal arrivals at a first set of input terminals of a logic module combinationally reaching a write port of a memory element, a second set of input terminals of the logic module combinationally reaching a control input of the memory element, and a set of output terminals of the logic module combinationally reached from a read port of the memory element. Such a method can include (1) computing a minimum delay value between each of the first set of input terminals and the write port; (2) computing a maximum delay value between each of the second set of input terminals and the control input; (3) assigning a ready time for the write port; (4) assigning a required ready time at each terminal of the first set of input terminals based on the ready time of the write port and the minimum delay value of the terminal; and (5) assigning a ready time at each terminal of the second set of input terminals based on the ready time of the write port and the maximum delay value of the terminal. In addition, for a memory element accessed from multiple domains, the method can include modelling the memory element as a collection of single domain read ports and one or more single domain write port. That method can further include (1) calculating a read access time for each of the single domain read port; and (2) calculating a ready time for each of the single domain read ports, the ready time being based on the latest departure time of departure times of terminals in the set of output terminals and the read access time. The initial read time for each terminal of the first set of input terminal can be determined by (1) calculating a write access time of the write port; and selecting a value based on the latest ready time of the single domain read ports and the write access port. The ready time for each terminal of the first set of input terminals can be further refined by the greater of the required ready time of the terminal and the ready time of the terminal. Delay elements can be inserted between the terminal and the write port based on the required ready time of the terminal and the initial ready time of the terminal.
Correct functional verification of any logic circuit with MTSD nets, latches or memory can be achieved using a combination of the above techniques.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.